GICv3 Distributor Control Register, GICD_CTLR (0x0000).
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uint32_t | raw |
| | Raw 32-bit register value.
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struct { | |
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bool enable_grp0: 1 | |
| | Enables Group 0 interrupts.
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bool enable_grp1ns: 1 | |
| | Enables Non-secure Group 1 interrupts.
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bool enable_grp1s: 1 | |
| | Enables Secure Group 1 interrupts. RES0 if are_s == 0.
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bool res0: 1 | |
| | Reserved.
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bool are_s: 1 | |
| | Affinity Routing Enable, Secure state.
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bool are_ns: 1 | |
| | Affinity Routing Enable, Non-secure state.
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bool ds: 1 | |
| | Disable Security. RAO/WI on implementations with a single security state.
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bool e1nwf: 1 | |
| | Enable 1-of-N Wakeup Functionality.
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uint32_t res1: 23 | |
| | Reserved (includes the nASSGIreq field).
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bool rwp: 1 | |
| | Register Write Pending. Read-only; poll until 0 after writes this field tracks.
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| }; | | |
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GICv3 Distributor Control Register, GICD_CTLR (0x0000).
Bit layout per Arm IHI 0069. On QEMU virt the GIC runs with a single security state (DS reads as 1, RAO/WI), in which case ARE_S/ARE_NS/ EnableGrp1S are not meaningful and only EnableGrp0/EnableGrp1NS/DS/RWP are relevant.
The documentation for this union was generated from the following file:
