gicd_isenabler_t Union Reference

GICD_ISENABLER<n> — Distributor Interrupt Set-Enable Registers (offset 0x0100 + 4n, RW) More...

Data Fields
uint32_t	raw
	Raw 32-bit register value.
struct {
uint32_t   enable: 32
	Bit n enables INTID (32*reg + n). Write 1 to enable, write 0 has no effect.
};

Detailed Description

GICD_ISENABLER<n> — Distributor Interrupt Set-Enable Registers (offset 0x0100 + 4n, RW)

Each bit enables forwarding of the corresponding SPI INTID. Register n covers INTIDs [32n+31 : 32n].

GICD_ISENABLER0 → INTIDs 0-31 (SGI/PPI range, RAZ/WI) GICD_ISENABLER1 → INTIDs 32-63 (SPIs start here) GICD_ISENABLER2 → INTIDs 64-95 ... and so on.

Writing 1 enables the interrupt. Writing 0 has no effect. Use GICD_ICENABLER<n> to disable. Resets to 0 on GIC reset.

---

The documentation for this union was generated from the following file:

• src/kernel/drivers/gicv3.c