GICv3 Distributor Type Register, GICD_TYPER (0x0004, RO).
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uint32_t | raw |
| | Raw 32-bit register value.
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struct { | |
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uint32_t itlinesnumber: 5 | |
| | (ITLinesNumber + 1) * 32 - 1 = highest SPI INTID supported.
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uint32_t cpunumber: 3 | |
| | Number of PEs visible with affinity routing disabled; unused once ARE is set.
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bool espi: 1 | |
| | 1 if the extended SPI range is implemented.
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bool nmi: 1 | |
| | 1 if Non-maskable Interrupt priorities are supported.
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bool security_extn: 1 | |
| | 1 if the GIC implements two security states. Reads as 0 when GICD_CTLR.DS == 1.
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uint32_t num_lpis: 5 | |
| | Number of LPIs supported. 0: determined by idbits instead. Otherwise, 2^(num_lpis+1) LPIs.
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bool mbis: 1 | |
| | 1 if message-based SPIs via GICD_SETSPI_NSR/CLRSPI_NSR are supported.
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bool lpis: 1 | |
| | 1 if LPIs are supported.
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bool dvis: 1 | |
| | 1 if direct injection of virtual LPIs is supported.
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uint32_t idbits: 5 | |
| | Number of physical interrupt identifier bits supported, minus 1.
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bool a3v: 1 | |
| | 1 if non-zero values of affinity level 3 are supported.
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bool no1n: 1 | |
| | 1 if 1-of-N SPI interrupt targeting is not supported.
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bool rss: 1 | |
| | 1 if the Range Selector field is supported in GICD_IROUTER<n> and ICC_SGI*R_EL1.
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uint32_t espi_range: 5 | |
| | If espi == 1, (espi_range + 1) * 32 extended SPIs are supported beyond INTID 4095.
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| }; | | |
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GICv3 Distributor Type Register, GICD_TYPER (0x0004, RO).
Bit layout per Arm IHI 0069. Fields relating to extended SPIs, LPIs, and the 1-of-N/range-selector extensions are decoded for completeness but are not exercised by this driver, which targets a single PE without an ITS.
The documentation for this union was generated from the following file:
