gicr_ipriorityr_t Union Reference

GICR_IPRIORITYR — Redistributor Interrupt Priority Registers (SGI frame, offset 0x0400-0x041C, RW) More...

Data Fields
uint32_t	raw
	Raw 32-bit register value.
struct {
uint32_t   prio_0: 8
	[7:0] Priority of INTID (4n+0).
uint32_t   prio_1: 8
	[15:8] Priority of INTID (4n+1).
uint32_t   prio_2: 8
	[23:16] Priority of INTID (4n+2).
uint32_t   prio_3: 8
	[31:24] Priority of INTID (4n+3).
};

Detailed Description

GICR_IPRIORITYR — Redistributor Interrupt Priority Registers (SGI frame, offset 0x0400-0x041C, RW)

Eight 32-bit registers, each holding the 8-bit priority of 4 INTIDs. Covers all 32 SGIs and PPIs (INTIDs 0-31).

Register n covers INTIDs [4n+3 : 4n]: GICR_IPRIORITYR0 → INTIDs 0- 3 (offset 0x0400) GICR_IPRIORITYR1 → INTIDs 4- 7 (offset 0x0404) GICR_IPRIORITYR2 → INTIDs 8-11 (offset 0x0408) GICR_IPRIORITYR3 → INTIDs 12-15 (offset 0x040C) GICR_IPRIORITYR4 → INTIDs 16-19 (offset 0x0410) GICR_IPRIORITYR5 → INTIDs 20-23 (offset 0x0414) GICR_IPRIORITYR6 → INTIDs 24-27 (offset 0x0418) GICR_IPRIORITYR7 → INTIDs 28-31 (offset 0x041C)

Lower value = higher priority. Only the high bits are implemented (determined by ICC_CTLR_EL1.PRIbits); unimplemented low bits are RAZ/WI.

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The documentation for this union was generated from the following file:

• src/kernel/drivers/gicv3.c