gicr_isenabler0_t Union Reference

GICR_ISENABLER0 — Redistributor Interrupt Set-Enable Register 0 (SGI frame, offset 0x0100, RW) More...

Data Fields
uint32_t	raw
	Raw 32-bit register value.
struct {
uint32_t   sgi_enable: 16
	[15:0] SGI enable bits (INTIDs 0-15). Reset to 0. Write 1 to enable forwarding of the corresponding SGI to the CPU interface. Write 0 has no effect.
uint32_t   ppi_enable: 16
	[31:16] PPI enable bits (INTIDs 16-31). Reset to 0. Write 1 to enable forwarding of the corresponding PPI to the CPU interface. Write 0 has no effect.
};

Detailed Description

GICR_ISENABLER0 — Redistributor Interrupt Set-Enable Register 0 (SGI frame, offset 0x0100, RW)

Each bit enables forwarding of the corresponding SGI or PPI INTID to the CPU interface for this PE.

Writing 1 enables forwarding. Writing 0 has no effect. Use GICR_ICENABLER0 to disable individual interrupts. Resets to 0 on GIC reset — all SGIs and PPIs are disabled by default and must be explicitly enabled by software.

Bit layout: [15:0] SGIs (INTIDs 0-15) : RW — reset to 0, write 1 to enable [31:16] PPIs (INTIDs 16-31) : RW — reset to 0, write 1 to enable

---

The documentation for this union was generated from the following file:

• src/kernel/drivers/gicv3.c