gicr_waker_t Union Reference

GICR_WAKER — Redistributor Wake Register (RD frame, offset 0x0014, RW) More...

Data Fields
uint32_t	raw
	Raw 32-bit register value.
struct {
bool   impl_defined_0: 1
	[0] Implementation-defined sleep bit. RES0 on most impls.
bool   processor_sleep: 1
	[1] ProcessorSleep (RW): Set by software to signal the PE is entering a low-power state. Clear this to wake the Redistributor. Must only be changed while ChildrenAsleep == 1.
bool   children_asleep: 1
	[2] ChildrenAsleep (RO): Set by hardware when all CPU interface child nodes have entered a quiescent state. Poll until this reads 0 after clearing ProcessorSleep.
uint32_t   res0: 28
	[30:3] Reserved.
bool   impl_defined_31: 1
	[31] Implementation-defined sleep bit. RES0 on most impls.
};

Detailed Description

GICR_WAKER — Redistributor Wake Register (RD frame, offset 0x0014, RW)

Controls and reflects the sleep/wake state of this Redistributor. The boot sequence requires clearing ProcessorSleep and then polling ChildrenAsleep until it reads 0 before the PE can receive interrupts.

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The documentation for this union was generated from the following file:

• src/kernel/drivers/gicv3.c