ICC_CTLR_EL1 — Interrupt Controller Control Register (EL1).
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uint64_t | raw |
| | Raw 64-bit register value.
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struct { | |
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bool cbpr: 1 | |
| | [0] CBPR: Common Binary Point Register. 0 = ICC_BPR0_EL1 and ICC_BPR1_EL1 are independent. 1 = ICC_BPR0_EL1 is used for both Group 0 and Group 1.
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bool eoi_mode: 1 | |
| | [1] EOImode: End of Interrupt mode. 0 = ICC_EOIR1_EL1 performs priority drop AND deactivation. 1 = ICC_EOIR1_EL1 performs priority drop only; deactivation requires a separate write to ICC_DIR_EL1.
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uint32_t res0_5_2: 4 | |
| | [5:2] Reserved.
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bool pmhe: 1 | |
| | [6] PMHE: Priority Mask Hint Enable. When 1, the priority mask register (ICC_PMR_EL1) is used as a hint for interrupt routing in power management scenarios. RAZ/WI if the implementation does not support this feature.
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uint32_t res0_7: 1 | |
| | [7] Reserved.
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uint32_t pri_bits: 3 | |
| | [10:8] PRIbits (RO): Number of priority bits implemented, minus one. A value of N means N+1 priority bits are implemented, giving 2^(N+1) priority levels. E.g. value of 4 means 4+1 = 5 bits = 32 priority levels.
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uint32_t id_bits: 3 | |
| | [13:11] IDbits (RO): Number of interrupt identifier bits supported. 0b000 = 16-bit, 0b001 = 24-bit.
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bool seis: 1 | |
| | [14] SEIS (RO): Supports generation of SEIs (System Error Interrupts) by the CPU interface.
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bool a3v: 1 | |
| | [15] A3V (RO): Affinity 3 Valid. When 1, non-zero Aff3 values are supported in SGI routing.
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uint32_t res0_17_16: 2 | |
| | [17:16] Reserved.
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bool rss: 1 | |
| | [18] RSS: Range Selector Support (RO). When 1, ICC_SGI0R_EL1 and ICC_SGI1R_EL1 support the RS field for targeting SGIs to PEs with Aff3 values 0-15 and 16-31.
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bool ext_range: 1 | |
| | [19] ExtRange: Extended INTID range supported (RO). When 1, extended SPI/PPI ranges (INTIDs 1024-8191) are supported by this CPU interface.
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uint64_t res0_63_20: 44 | |
| | [63:20] Reserved.
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| }; | | |
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ICC_CTLR_EL1 — Interrupt Controller Control Register (EL1).
Controls the behavior of the CPU interface for the current Security state. Key fields are EOImode (split vs priority-drop-and-deactivate) and read-only capability fields populated by hardware.
Verified against ARM IHI0069 (GICv3 Architecture Specification).
The documentation for this union was generated from the following file:
1.9.8