icc_pmr_el1_t Union Reference

ICC_PMR_EL1 — Interrupt Controller Priority Mask Register (EL1). More...

Data Fields
uint64_t	raw
	Raw 64-bit register value.
struct {
uint32_t   priority: 8
	[7:0] Priority: The priority mask level. Interrupts with a priority value >= this threshold are suppressed. 0x00 = No interrupts allowed through. 0xFF = All interrupts allowed through.
uint64_t   res0: 56
	[63:8] Reserved.
};

Detailed Description

ICC_PMR_EL1 — Interrupt Controller Priority Mask Register (EL1).

Sets the minimum priority threshold for interrupt delivery to the PE. Only interrupts with a priority numerically LESS THAN this value are forwarded to the PE. Set to 0xFF to allow all priorities through.

Note: In a two-security-state system, Non-secure reads/writes to this register may see a shifted view of the priority (bit 7 forced to 1).

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The documentation for this union was generated from the following file:

• src/kernel/drivers/gicv3.c