ICC_SRE_EL1 — Interrupt Controller System Register Enable (EL1). More...

Data Fields
uint64_t	raw
	Raw 64-bit register value.

struct {

bool sre: 1
	[0] SRE: System Register Enable. Must be 1 to use ICC_* system registers. When 0, GICC memory-mapped registers are used instead. RAO/WI if EL2/EL3 have already forced it enabled.

bool dfb: 1
	[1] DFB: Disable FIQ Bypass. When 1, FIQ signals are not bypassed to the CPU. Should be set to 1 in most OS kernels.

bool dib: 1
	[2] DIB: Disable IRQ Bypass. When 1, IRQ signals are not bypassed to the CPU. Should be set to 1 in most OS kernels.

uint64_t res0: 61
	[63:3] Reserved.

};

Detailed Description

ICC_SRE_EL1 — Interrupt Controller System Register Enable (EL1).

Controls whether the CPU interface registers are accessed via the memory-mapped GICC interface or the AArch64 ICC_* system registers. SRE must be set to 1 before any other ICC_* register can be used.

Note: If EL3 is present, ICC_SRE_EL3.SRE must also be set first, and ICC_SRE_EL2.SRE/Enable must be set to allow EL1 access.

The documentation for this union was generated from the following file:

src/kernel/drivers/gicv3.c

Data Fields

Detailed Description