mair_normal_attr_t Struct Reference

MAIR attribute byte layout for Normal (cacheable) memory. More...

Data Fields
uint8_t	inner_write_alloc: 1
uint8_t	inner_read_alloc: 1
uint8_t	inner_write_back: 1
uint8_t	inner_non_transient: 1
uint8_t	outer_write_alloc: 1
uint8_t	outer_read_alloc: 1
uint8_t	outer_write_back: 1
uint8_t	outer_non_transient: 1

Detailed Description

MAIR attribute byte layout for Normal (cacheable) memory.

The byte is split into two 4-bit cache-policy nibbles:

• Inner nibble [3:0]: policy seen by the CPU's own cache hierarchy.
• Outer nibble [7:4]: policy seen by the outer (system-level) cache.

Per-nibble encoding: 0b0000 = Device / invalid (only legal for outer nibble to mark Device) 0b0100 = Non-cacheable 0bNWRT = Cacheable: N=Non-transient, W=Write-Back, R=Read-Alloc, T=Write-Alloc

Field Documentation

inner_non_transient

uint8_t mair_normal_attr_t::inner_non_transient

[3] Inner: 1=Non-transient, 0=Transient hint.

inner_read_alloc

uint8_t mair_normal_attr_t::inner_read_alloc

[1] Inner Read-Allocate on cache miss.

inner_write_alloc

uint8_t mair_normal_attr_t::inner_write_alloc

[0] Inner Write-Allocate on cache miss.

inner_write_back

uint8_t mair_normal_attr_t::inner_write_back

[2] Inner policy: 1=Write-Back, 0=Write-Through.

outer_non_transient

uint8_t mair_normal_attr_t::outer_non_transient

[7] Outer: 1=Non-transient, 0=Transient hint.

outer_read_alloc

uint8_t mair_normal_attr_t::outer_read_alloc

[5] Outer Read-Allocate on cache miss.

outer_write_alloc

uint8_t mair_normal_attr_t::outer_write_alloc

[4] Outer Write-Allocate on cache miss.

outer_write_back

uint8_t mair_normal_attr_t::outer_write_back

[6] Outer policy: 1=Write-Back, 0=Write-Through.

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The documentation for this struct was generated from the following file:

• src/kernel/mmu/mmu.c