Implementation of Memory Management Unit utilities. More...

#include "mmu/mmu.h"
#include "asm/asm_helper.h"
#include "mem_layout/mem_layout.h"
#include "utils/kprintf.h"
#include <stdint.h>

Include dependency graph for mmu.c:

Data Structures
struct	mair_device_attr_t
	MAIR attribute byte layout for Device memory. More...

struct	mair_normal_attr_t
	MAIR attribute byte layout for Normal (cacheable) memory. More...

struct	mair_attr_t
	Single MAIR attribute slot (one byte). More...

struct	mair_reg_t
	MAIR_EL1 register — 8 independent attribute slots. More...

struct	sctlr_el1_t
	SCTLR_EL1 — System Control Register, EL1. More...

Typedefs
typedef struct mair_device_attr_t	mair_device_attr_t
	MAIR attribute byte layout for Device memory.

typedef struct mair_normal_attr_t	mair_normal_attr_t
	MAIR attribute byte layout for Normal (cacheable) memory.

typedef struct mair_attr_t	mair_attr_t
	Single MAIR attribute slot (one byte).

typedef struct mair_reg_t	mair_reg_t
	MAIR_EL1 register — 8 independent attribute slots.

typedef struct sctlr_el1_t	sctlr_el1_t
	SCTLR_EL1 — System Control Register, EL1.

Enumerations
enum	device_type { DEVICE_nGnRnE = 0b00 , DEVICE_nGnRE = 0b01 , DEVICE_nGRE = 0b10 , DEVICE_GRE = 0b11 }
	Device memory subtype — encodes bits[3:2] of a Device attribute byte. More...

enum	tcr_cacheability { TCR_CACHE_NON_CACHEABLE = 0b00 , TCR_CACHE_WB_RA_WA = 0b01 , TCR_CACHE_WT_RA_NWA = 0b10 , TCR_CACHE_WB_RA_NWA = 0b11 }
	Inner/Outer cacheability encoding for TCR_EL1 IRGN/ORGN fields. More...

enum	tcr_shareability { TCR_SH_NON_SHAREABLE = 0b00 , TCR_SH_RESERVED = 0b01 , TCR_SH_OUTER_SHAREABLE = 0b10 , TCR_SH_INNER_SHAREABLE = 0b11 }
	Shareability domain encoding for TCR_EL1 SH0/SH1 fields. More...

enum	tcr_tg0 { TCR_TG0_4KB = 0b00 , TCR_TG0_64KB = 0b01 , TCR_TG0_16KB = 0b10 }
	Translation granule size for TTBR0_EL1 (TG0 field, bits[15:14]). More...

enum	tcr_tg1 { TCR_TG1_16KB = 0b01 , TCR_TG1_4KB = 0b10 , TCR_TG1_64KB = 0b11 }
	Translation granule size for TTBR1_EL1 (TG1 field, bits[31:30]). More...

enum	tcr_ips { TCR_IPS_32BIT = 0b000 , TCR_IPS_36BIT = 0b001 , TCR_IPS_40BIT = 0b010 , TCR_IPS_44BIT = 0b011 , TCR_IPS_48BIT = 0b100 , TCR_IPS_52BIT = 0b101 }
	Intermediate Physical Address size (IPS field, bits[34:32]). More...

Functions
bool	enable_mmu (page_table_t id_map_root, page_table_t kernel_map_root)
	Configure system registers and enable the AArch64 EL1 MMU.

Detailed Description

Implementation of Memory Management Unit utilities.

Provides architecture-specific mmu setup.

Author: Abhin Parekadan Jose

Date: 2026-05-25

Typedef Documentation

◆ mair_attr_t

typedef struct mair_attr_t mair_attr_t

Single MAIR attribute slot (one byte).

Overlays a raw byte with typed views for Device or Normal memory. Which union member is active is determined by the upper nibble: device.res0_7_4 == 0b0000 → Device memory. Otherwise → Normal memory.

◆ mair_device_attr_t

typedef struct mair_device_attr_t mair_device_attr_t

MAIR attribute byte layout for Device memory.

Bits[7:4] must be 0b0000 to mark this slot as Device memory. Bits[3:2] select the device subtype (see device_type). Bit[1] is RES0. Bit[0] is the XS bit (FEAT_XS memory-tagging share domain); RES0 otherwise.

◆ mair_normal_attr_t

typedef struct mair_normal_attr_t mair_normal_attr_t

MAIR attribute byte layout for Normal (cacheable) memory.

The byte is split into two 4-bit cache-policy nibbles:

Inner nibble [3:0]: policy seen by the CPU's own cache hierarchy.
Outer nibble [7:4]: policy seen by the outer (system-level) cache.

Per-nibble encoding: 0b0000 = Device / invalid (only legal for outer nibble to mark Device) 0b0100 = Non-cacheable 0bNWRT = Cacheable: N=Non-transient, W=Write-Back, R=Read-Alloc, T=Write-Alloc

◆ mair_reg_t

typedef struct mair_reg_t mair_reg_t

MAIR_EL1 register — 8 independent attribute slots.

AttrIndx[2:0] in a leaf page/block descriptor selects which slot applies to that mapping (see mem_type_t for this kernel's slot assignments).

◆ sctlr_el1_t

typedef struct sctlr_el1_t sctlr_el1_t

SCTLR_EL1 — System Control Register, EL1.

Controls the EL1&0 execution environment: MMU, caches, alignment checks, pointer authentication, branch target identification, and memory tagging.

Reference: ARMv8/ARMv9 ARM DDI 0601, section SCTLR_EL1.

Enumeration Type Documentation

◆ device_type

enum device_type

Device memory subtype — encodes bits[3:2] of a Device attribute byte.

G = Gathering (multiple accesses may be merged into one transaction) R = Reordering (accesses to the same device may be reordered) E = Early write acknowledgement (write can be acknowledged before device)

Enumerator
DEVICE_nGnRnE	Non-Gathering, Non-Reordering, No early ack
DEVICE_nGnRE	Non-Gathering, Non-Reordering, Early ack
DEVICE_nGRE	Non-Gathering, Reordering, Early ack
DEVICE_GRE	Gathering, Reordering, Early ack

◆ tcr_cacheability

enum tcr_cacheability

Inner/Outer cacheability encoding for TCR_EL1 IRGN/ORGN fields.

Applies to IRGN0, ORGN0 (TTBR0 walks) and IRGN1, ORGN1 (TTBR1 walks).

Enumerator
TCR_CACHE_NON_CACHEABLE	Normal, Non-cacheable.
TCR_CACHE_WB_RA_WA	Normal, Write-Back Read-Alloc Write-Alloc Cacheable.
TCR_CACHE_WT_RA_NWA	Normal, Write-Through Read-Alloc No Write-Alloc Cacheable.
TCR_CACHE_WB_RA_NWA	Normal, Write-Back Read-Alloc No Write-Alloc Cacheable.

◆ tcr_ips

enum tcr_ips

Intermediate Physical Address size (IPS field, bits[34:32]).

Enumerator
TCR_IPS_32BIT	32-bit PA (4 GB).
TCR_IPS_36BIT	36-bit PA (64 GB).
TCR_IPS_40BIT	40-bit PA (1 TB).
TCR_IPS_44BIT	44-bit PA (16 TB).
TCR_IPS_48BIT	48-bit PA (256 TB).
TCR_IPS_52BIT	52-bit PA (4 PB, FEAT_LPA).

◆ tcr_shareability

enum tcr_shareability

Shareability domain encoding for TCR_EL1 SH0/SH1 fields.

Applies to SH0 (TTBR0 walks) and SH1 (TTBR1 walks).

Enumerator
TCR_SH_NON_SHAREABLE	Non-Shareable.
TCR_SH_RESERVED	RESERVED — must not be used.
TCR_SH_OUTER_SHAREABLE	Outer Shareable.
TCR_SH_INNER_SHAREABLE	Inner Shareable.

◆ tcr_tg0

enum tcr_tg0

Translation granule size for TTBR0_EL1 (TG0 field, bits[15:14]).

Enumerator
TCR_TG0_4KB	4 KB granule.
TCR_TG0_64KB	64 KB granule.
TCR_TG0_16KB	16 KB granule.

◆ tcr_tg1

enum tcr_tg1

Translation granule size for TTBR1_EL1 (TG1 field, bits[31:30]).

Note: The encoding is different from tcr_tg0.

Enumerator
TCR_TG1_16KB	16 KB granule.
TCR_TG1_4KB	4 KB granule.
TCR_TG1_64KB	64 KB granule.

Function Documentation

◆ enable_mmu()

bool enable_mmu	(	page_table_t *	id_map_root,
		page_table_t *	kernel_map_root
	)

Configure system registers and enable the AArch64 EL1 MMU.

Performs the full MMU bring-up sequence in order:

Programs MAIR_EL1 with the kernel's two memory attribute slots (slot 0 = Device-nGnRnE, slot 1 = Normal WB-RWA Cacheable).
Configures TCR_EL1 for a 48-bit VA space (T0SZ=16), 4 KB granule, inner/outer write-back cacheable table walks, inner-shareable domain, and 40-bit IPS
Writes the physical address of id_map_root into TTBR0_EL1.
Writes the physical address of kernel_map_root into TTBR1_EL1.
Enables the MMU (M), D-cache (C), and I-cache (I) in SCTLR_EL1

Parameters

id_map_root	Pointer to the id_map_root (L0) page table whose physical address is loaded into TTBR0_EL1. Must not be NULL.
kernel_map_root	Pointer to the kernel_map_root (L1) page table whose physical address is loaded into TTBR1_EL1. Must not be NULL.

Returns: true MMU enabled successfully.; false id_map_root or kernel_map_root was NULL.

Data Structures

Typedefs

Enumerations

Functions