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Kernelite 0.1.0
Kernelite is a minimalist, educational operating system kernel built from scratch. The project aims to recreate core components of the Linux architecture to explore the fundamentals of operating system design and hardware-software interaction.
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SCTLR_EL1 — System Control Register, EL1. More...
Data Fields | ||
| union { | ||
| uint64_t value | ||
| struct { | ||
| uint64_t m: 1 | ||
| uint64_t a: 1 | ||
| uint64_t c: 1 | ||
| uint64_t sa: 1 | ||
| uint64_t sa0: 1 | ||
| uint64_t cp15ben: 1 | ||
| uint64_t naa: 1 | ||
| uint64_t itd: 1 | ||
| uint64_t sed: 1 | ||
| uint64_t uma: 1 | ||
| uint64_t enrctx: 1 | ||
| uint64_t eos: 1 | ||
| uint64_t i: 1 | ||
| uint64_t endb: 1 | ||
| uint64_t dze: 1 | ||
| uint64_t uct: 1 | ||
| uint64_t ntwi: 1 | ||
| uint64_t res0_17: 1 | ||
| uint64_t ntwe: 1 | ||
| uint64_t wxn: 1 | ||
| uint64_t tscxt: 1 | ||
| uint64_t iesb: 1 | ||
| uint64_t eis: 1 | ||
| uint64_t span: 1 | ||
| uint64_t e0e: 1 | ||
| uint64_t ee: 1 | ||
| uint64_t uci: 1 | ||
| uint64_t enda: 1 | ||
| uint64_t ntlsmd: 1 | ||
| uint64_t lsmaoe: 1 | ||
| uint64_t enib: 1 | ||
| uint64_t enia: 1 | ||
| uint64_t res0_34_32: 3 | ||
| uint64_t bt0: 1 | ||
| uint64_t bt1: 1 | ||
| uint64_t itfsb: 1 | ||
| uint64_t tcf0: 2 | ||
| uint64_t tcf: 2 | ||
| uint64_t ata0: 1 | ||
| uint64_t ata: 1 | ||
| uint64_t dssbs: 1 | ||
| uint64_t tweden: 1 | ||
| uint64_t twedel: 4 | ||
| uint64_t res0_53_50: 4 | ||
| uint64_t enasr: 1 | ||
| uint64_t enas0: 1 | ||
| uint64_t enals: 1 | ||
| uint64_t epan: 1 | ||
| uint64_t res0_63_58: 6 | ||
| } | ||
| }; | ||
SCTLR_EL1 — System Control Register, EL1.
Controls the EL1&0 execution environment: MMU, caches, alignment checks, pointer authentication, branch target identification, and memory tagging.
Reference: ARMv8/ARMv9 ARM DDI 0601, section SCTLR_EL1.
| uint64_t sctlr_el1_t::a |
[1] A — Alignment fault enable. 1=fault on unaligned access.
| uint64_t sctlr_el1_t::ata |
[43] ATA — EL1 Allocation Tag Access enable (FEAT_MTE2).
| uint64_t sctlr_el1_t::ata0 |
[42] ATA0 — EL0 Allocation Tag Access enable (FEAT_MTE2).
| uint64_t sctlr_el1_t::bt0 |
[35] BT0 — PAC Branch Type Compatibility at EL0 (FEAT_BTI). 1=PACIASP/PACIBSP not compatible with PSTATE.BTYPE==0b11 at EL0.
| uint64_t sctlr_el1_t::bt1 |
[36] BT1 — PAC Branch Type Compatibility at EL1 (FEAT_BTI). 1=PACIASP/PACIBSP not compatible with PSTATE.BTYPE==0b11 at EL1.
| uint64_t sctlr_el1_t::c |
[2] C — Data cache enable. 0=off, 1=on.
| uint64_t sctlr_el1_t::cp15ben |
[5] CP15BEN — CP15 barrier instruction enable (FEAT_CP15BEN).
| uint64_t sctlr_el1_t::dssbs |
[44] DSSBS — Default PSTATE.SSBS value on exception entry to EL1 (FEAT_SSBS).
| uint64_t sctlr_el1_t::dze |
[14] DZE — EL0 access to DC ZVA instruction enable.
| uint64_t sctlr_el1_t::e0e |
[24] E0E — EL0 data accesses are big-endian.
| uint64_t sctlr_el1_t::ee |
[25] EE — Exception endianness. 0=little-endian, 1=big-endian.
| uint64_t sctlr_el1_t::eis |
[22] EIS — Exception entry is a context synchronization event (FEAT_ExS).
| uint64_t sctlr_el1_t::enals |
[56] EnALS — Trap EL0 LD64B/ST64B instructions to EL1 (FEAT_LS64).
| uint64_t sctlr_el1_t::enas0 |
[55] EnAS0 — Trap EL0 ST64BV0 instruction to EL1 (FEAT_LS64).
| uint64_t sctlr_el1_t::enasr |
[54] EnASR — Trap EL0 ST64BV instruction to EL1 (FEAT_LS64).
| uint64_t sctlr_el1_t::enda |
[27] EnDA — Pointer authentication using APDAKey_EL1 enable (FEAT_PAuth).
| uint64_t sctlr_el1_t::endb |
[13] EnDB — Pointer authentication using APDBKey_EL1 enable (FEAT_PAuth).
| uint64_t sctlr_el1_t::enia |
[31] EnIA — Pointer authentication using APIAKey_EL1 enable (FEAT_PAuth).
| uint64_t sctlr_el1_t::enib |
[30] EnIB — Pointer authentication using APIBKey_EL1 enable (FEAT_PAuth).
| uint64_t sctlr_el1_t::enrctx |
[10] EnRCTX — EL0 access to FEAT_RCPC instructions enable.
| uint64_t sctlr_el1_t::eos |
[11] EOS — Exception exit is a context synchronization event (FEAT_ExS).
| uint64_t sctlr_el1_t::epan |
[57] EPAN — Enhanced Privileged Access Never (FEAT_PAN3). 1=EL1 data access to EL0-accessible pages generates Permission fault.
| uint64_t sctlr_el1_t::i |
[12] I — Instruction cache enable. 0=off, 1=on.
| uint64_t sctlr_el1_t::iesb |
[21] IESB — Implicit Error Synchronization Barrier enable (FEAT_IESB).
| uint64_t sctlr_el1_t::itd |
[7] ITD — IT instruction disable for T32 at EL0.
| uint64_t sctlr_el1_t::itfsb |
[37] ITFSB — Implicit Tag Fault Synchronization Barrier on EL1 entry (FEAT_MTE2).
| uint64_t sctlr_el1_t::lsmaoe |
[29] LSMAOE — LDM/STM atomicity and ordering enable (FEAT_LSMAOC).
| uint64_t sctlr_el1_t::m |
[0] M — MMU enable for EL1&0 stage 1 translation. 0=off, 1=on.
| uint64_t sctlr_el1_t::naa |
[6] nAA — Non-aligned access enable (FEAT_LSE2). 1=hardware handles unaligned accesses at EL1/EL0.
| uint64_t sctlr_el1_t::ntlsmd |
[28] nTLSMD — No trap LDM/STM/LDP/STP to Device-nGRE/nGnRE/nGnRnE (FEAT_LSMAOC).
| uint64_t sctlr_el1_t::ntwe |
[18] nTWE — Do not trap EL0 WFE instructions to EL1.
| uint64_t sctlr_el1_t::ntwi |
[16] nTWI — Do not trap EL0 WFI instructions to EL1.
| uint64_t sctlr_el1_t::res0_17 |
[17] RES0.
| uint64_t sctlr_el1_t::res0_34_32 |
[34:32] RES0.
| uint64_t sctlr_el1_t::res0_53_50 |
[53:50] RES0.
| uint64_t sctlr_el1_t::res0_63_58 |
[63:58] RES0.
| uint64_t sctlr_el1_t::sa |
[3] SA — EL1 stack pointer alignment check enable.
| uint64_t sctlr_el1_t::sa0 |
[4] SA0 — EL0 stack pointer alignment check enable.
| uint64_t sctlr_el1_t::sed |
[8] SED — SETEND instruction disable.
| uint64_t sctlr_el1_t::span |
[23] SPAN — Set PAN on exception entry to EL1 (FEAT_PAN). 0=PSTATE.PAN set to 1 on entry, 1=PSTATE.PAN unchanged.
| uint64_t sctlr_el1_t::tcf |
[41:40] TCF — EL1 Tag Check Fault mode (FEAT_MTE2). 00=no effect, 01=sync exception, 10=async accumulated, 11=sync reads/async writes (FEAT_MTE3).
| uint64_t sctlr_el1_t::tcf0 |
[39:38] TCF0 — EL0 Tag Check Fault mode (FEAT_MTE2). 00=no effect, 01=sync exception, 10=async accumulated, 11=sync reads/async writes (FEAT_MTE3).
| uint64_t sctlr_el1_t::tscxt |
[20] TSCXT — Trap EL0 access to SCXTNUM_EL0 (FEAT_CSV2_2).
| uint64_t sctlr_el1_t::twedel |
[49:46] TWEDEL — TWE Delay value;trap delay = 2^(TWEDEL+8) cycles (FEAT_TWED).
| uint64_t sctlr_el1_t::tweden |
[45] TWEDEn — TWE Delay enable (FEAT_TWED).
| uint64_t sctlr_el1_t::uci |
[26] UCI — EL0 cache maintenance instructions (DC CVAU, IC IVAU, etc.) enable.
| uint64_t sctlr_el1_t::uct |
[15] UCT — EL0 access to CTR_EL0 enable.
| uint64_t sctlr_el1_t::uma |
[9] UMA — User Mask Access: 1=EL0 may read/write DAIF.
| uint64_t sctlr_el1_t::value |
Raw 64-bit register value for MRS/MSR.
| uint64_t sctlr_el1_t::wxn |
[19] WXN — Write permission implies Execute-Never at EL1.
1.9.8