mmu.h File Reference

Memory Management Unit utilities. More...

#include "page_table/page_table.h"
#include <stdint.h>

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Data Structures
struct	tcr_reg_t
	TCR_EL1 — Translation Control Register, EL1. More...

Typedefs
typedef struct tcr_reg_t	tcr_reg_t
	TCR_EL1 — Translation Control Register, EL1.

Functions
bool	enable_mmu (page_table_t *id_map_root, page_table_t *kernel_map_root)
	Configure system registers and enable the AArch64 EL1 MMU.

Detailed Description

Memory Management Unit utilities.

Provides architecture-specific mmu setup.

Author

Abhin Parekadan Jose

Date

2026-05-25

Typedef Documentation

tcr_reg_t

typedef struct tcr_reg_t tcr_reg_t

TCR_EL1 — Translation Control Register, EL1.

Controls the stage 1 translation regime for EL0 and EL1. TTBR0_EL1 governs the lower VA range [0, 2^(64-T0SZ)). TTBR1_EL1 governs the upper VA range [2^(64-T1SZ), 2^64).

Reference: ARMv8/ARMv9 ARM, section D19.2.131 TCR_EL1.

Function Documentation

enable_mmu()

bool enable_mmu	(	page_table_t *	id_map_root,
		page_table_t *	kernel_map_root
	)

Configure system registers and enable the AArch64 EL1 MMU.

Performs the full MMU bring-up sequence in order:

1. Programs MAIR_EL1 with the kernel's two memory attribute slots (slot 0 = Device-nGnRnE, slot 1 = Normal WB-RWA Cacheable).
2. Configures TCR_EL1 for a 48-bit VA space (T0SZ=16), 4 KB granule, inner/outer write-back cacheable table walks, inner-shareable domain, and 40-bit IPS
3. Writes the physical address of id_map_root into TTBR0_EL1.
4. Writes the physical address of kernel_map_root into TTBR1_EL1.
5. Enables the MMU (M), D-cache (C), and I-cache (I) in SCTLR_EL1

Parameters

id_map_root	Pointer to the id_map_root (L0) page table whose physical address is loaded into TTBR0_EL1. Must not be NULL.
kernel_map_root	Pointer to the kernel_map_root (L1) page table whose physical address is loaded into TTBR1_EL1. Must not be NULL.

Returns

true MMU enabled successfully.

false id_map_root or kernel_map_root was NULL.