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Kernelite 0.1.0
Kernelite is a minimalist, educational operating system kernel built from scratch. The project aims to recreate core components of the Linux architecture to explore the fundamentals of operating system design and hardware-software interaction.
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TCR_EL1 — Translation Control Register, EL1. More...
#include <mmu.h>
Data Fields | ||
| union { | ||
| uint64_t value | ||
| struct { | ||
| uint64_t t0sz: 6 | ||
| uint64_t res0_6: 1 | ||
| uint64_t epd0: 1 | ||
| uint64_t irgn0: 2 | ||
| uint64_t orgn0: 2 | ||
| uint64_t sh0: 2 | ||
| uint64_t tg0: 2 | ||
| uint64_t t1sz: 6 | ||
| uint64_t a1: 1 | ||
| uint64_t epd1: 1 | ||
| uint64_t irgn1: 2 | ||
| uint64_t orgn1: 2 | ||
| uint64_t sh1: 2 | ||
| uint64_t tg1: 2 | ||
| uint64_t ips: 3 | ||
| uint64_t res0_35: 1 | ||
| uint64_t as: 1 | ||
| uint64_t tbi0: 1 | ||
| uint64_t tbi1: 1 | ||
| uint64_t ha: 1 | ||
| uint64_t hd: 1 | ||
| uint64_t hpd0: 1 | ||
| uint64_t hpd1: 1 | ||
| uint64_t hwu059: 1 | ||
| uint64_t hwu060: 1 | ||
| uint64_t hwu061: 1 | ||
| uint64_t hwu062: 1 | ||
| uint64_t hwu159: 1 | ||
| uint64_t hwu160: 1 | ||
| uint64_t hwu161: 1 | ||
| uint64_t hwu162: 1 | ||
| uint64_t tbid0: 1 | ||
| uint64_t tbid1: 1 | ||
| uint64_t nfd0: 1 | ||
| uint64_t nfd1: 1 | ||
| uint64_t e0pd0: 1 | ||
| uint64_t e0pd1: 1 | ||
| uint64_t tcma0: 1 | ||
| uint64_t tcma1: 1 | ||
| uint64_t ds: 1 | ||
| uint64_t mtx0: 1 | ||
| uint64_t mtx1: 1 | ||
| uint64_t res0_63_62: 2 | ||
| } | ||
| Fields of the TCR_EL1 register. | ||
| }; | ||
TCR_EL1 — Translation Control Register, EL1.
Controls the stage 1 translation regime for EL0 and EL1. TTBR0_EL1 governs the lower VA range [0, 2^(64-T0SZ)). TTBR1_EL1 governs the upper VA range [2^(64-T1SZ), 2^64).
Reference: ARMv8/ARMv9 ARM, section D19.2.131 TCR_EL1.
| uint64_t tcr_reg_t::a1 |
[22] A1 — ASID from TTBR0_EL1 (0) or TTBR1_EL1 (1).
| uint64_t tcr_reg_t::as |
[36] AS — ASID size: 0=8-bit, 1=16-bit. RES0 if the implementation only supports 8-bit ASIDs.
| uint64_t tcr_reg_t::ds |
[59] DS — Enable 52-bit OA in 4KB/16KB granule descriptors (FEAT_LPA2). RES0 for 64KB granule.
| uint64_t tcr_reg_t::e0pd0 |
[55] E0PD0 — EL0 TTBR0 access generates level 0 Translation Fault.
| uint64_t tcr_reg_t::e0pd1 |
[56] E0PD1 — EL0 TTBR1 access generates level 0 Translation Fault.
| uint64_t tcr_reg_t::epd0 |
[7] EPD0 — 0=walk TTBR0, 1=fault on TTBR0 miss.
| uint64_t tcr_reg_t::epd1 |
[23] EPD1 — 0=walk TTBR1, 1=fault on TTBR1 miss.
| uint64_t tcr_reg_t::ha |
[39] HA — Hardware Access Flag update enable (FEAT_HAF).
| uint64_t tcr_reg_t::hd |
[40] HD — Hardware Dirty state update enable (FEAT_HAFDBS). Effective only when HA == 1.
| uint64_t tcr_reg_t::hpd0 |
[41] HPD0 — Disable APTable/PXNTable/UXNTable for TTBR0 walks.
| uint64_t tcr_reg_t::hpd1 |
[42] HPD1 — Disable APTable/PXNTable/UXNTable for TTBR1 walks.
| uint64_t tcr_reg_t::hwu059 |
[43] HWU059 — HW use of descriptor bit[59] for TTBR0 (FEAT_HPDS2).
| uint64_t tcr_reg_t::hwu060 |
[44] HWU060 — HW use of descriptor bit[60] for TTBR0 (FEAT_HPDS2).
| uint64_t tcr_reg_t::hwu061 |
[45] HWU061 — HW use of descriptor bit[61] for TTBR0 (FEAT_HPDS2).
| uint64_t tcr_reg_t::hwu062 |
[46] HWU062 — HW use of descriptor bit[62] for TTBR0 (FEAT_HPDS2).
| uint64_t tcr_reg_t::hwu159 |
[47] HWU159 — HW use of descriptor bit[59] for TTBR1 (FEAT_HPDS2).
| uint64_t tcr_reg_t::hwu160 |
[48] HWU160 — HW use of descriptor bit[60] for TTBR1 (FEAT_HPDS2).
| uint64_t tcr_reg_t::hwu161 |
[49] HWU161 — HW use of descriptor bit[61] for TTBR1 (FEAT_HPDS2).
| uint64_t tcr_reg_t::hwu162 |
[50] HWU162 — HW use of descriptor bit[62] for TTBR1 (FEAT_HPDS2).
| uint64_t tcr_reg_t::ips |
[34:32] IPS — Intermediate PA size (see tcr_ips).
| uint64_t tcr_reg_t::irgn0 |
[9:8] IRGN0 — Inner cacheability of TTBR0 table walks (see tcr_cacheability).
| uint64_t tcr_reg_t::irgn1 |
[25:24] IRGN1 — Inner cacheability of TTBR1 table walks (see tcr_cacheability).
| uint64_t tcr_reg_t::mtx0 |
[60] MTX0 — Canonical address tagging for TTBR0 region.
| uint64_t tcr_reg_t::mtx1 |
[61] MTX1 — Canonical address tagging for TTBR1 region.
| uint64_t tcr_reg_t::nfd0 |
[53] NFD0 — Non-fault walk disable for TTBR0 (FEAT_SVE).
| uint64_t tcr_reg_t::nfd1 |
[54] NFD1 — Non-fault walk disable for TTBR1 (FEAT_SVE).
| uint64_t tcr_reg_t::orgn0 |
[11:10] ORGN0 — Outer cacheability of TTBR0 table walks (see tcr_cacheability).
| uint64_t tcr_reg_t::orgn1 |
[27:26] ORGN1 — Outer cacheability of TTBR1 table walks (see tcr_cacheability).
| uint64_t tcr_reg_t::res0_35 |
[35] RES0.
| uint64_t tcr_reg_t::res0_6 |
[6] RES0.
| uint64_t tcr_reg_t::res0_63_62 |
[63:62] RES0.
| uint64_t tcr_reg_t::sh0 |
[13:12] SH0 — Shareability of TTBR0 table walks (see tcr_shareability).
| uint64_t tcr_reg_t::sh1 |
[29:28] SH1 — Shareability of TTBR1 table walks (see tcr_shareability).
| uint64_t tcr_reg_t::t0sz |
[5:0] T0SZ — VA size = 2^(64-T0SZ); 16 = 48-bit space.
| uint64_t tcr_reg_t::t1sz |
[21:16] T1SZ — VA size = 2^(64-T1SZ) for TTBR1 region.
| uint64_t tcr_reg_t::tbi0 |
[37] TBI0 — Top byte of TTBR0 addresses ignored for address matching.
| uint64_t tcr_reg_t::tbi1 |
[38] TBI1 — Top byte of TTBR1 addresses ignored for address matching.
| uint64_t tcr_reg_t::tbid0 |
[51] TBID0 — TBI0 applies to data accesses only for TTBR0.
| uint64_t tcr_reg_t::tbid1 |
[52] TBID1 — TBI1 applies to data accesses only for TTBR1.
| uint64_t tcr_reg_t::tcma0 |
[57] TCMA0 — Unchecked accesses when addr[59:55]=0b00000 (FEAT_MTE2).
| uint64_t tcr_reg_t::tcma1 |
[58] TCMA1 — Unchecked accesses when addr[59:55]=0b11111 (FEAT_MTE2).
| uint64_t tcr_reg_t::tg0 |
[15:14] TG0 — Granule size for TTBR0 (see tcr_tg0).
| uint64_t tcr_reg_t::tg1 |
[31:30] TG1 — Granule size for TTBR1 (see tcr_tg1).
| uint64_t tcr_reg_t::value |
Raw 64-bit register value for MRS/MSR.
1.9.8